The present invention relates to a clock generation technology used in a semiconductor integrated circuit device, and more particularly to a technology that is effective in generating a frequency modulation clock to slightly vary the frequency of a clock signal.
In recent years, in semiconductor integrated circuit devices such as microcomputers, it has been increasingly required to incorporate a spread spectrum clock generator (SSCG) that, when clocks are generated, generates so-called a spread spectrum clock (SSC) which is a frequency modulation clock in order to cope with electromagnetic interference (EMI).
The SSC is used to decrease EMI by slightly varying the frequency of a clock signal to reduce the peak value of the frequency spectrum of the clock signal and thereby reduce radiation noise.
Some semiconductor integrated circuit devices have not only circuit blocks such as a CPU which can be operated by the SSC but also circuit blocks for which the SSC cannot be used; in this case, it is necessary to generate two types of clocks. The circuit blocks for which the SSC cannot be used include, for example, interfaces such as USB, FLexRay and CAN.
When two types of clocks are generated in the semiconductor integrated circuit device as described above, it is common that the SSCG for generating the SSC and a PLL (phase locked loop) for generating a pure clock other than the SSC are used together.
In general, the PLL includes a phase comparator, a charge pump circuit, a low-pass filter, a voltage controlled oscillator (VCO) and a feedback frequency divider; as an output clock output from the PLL, a clock having N times the frequency of a reference input clock is output. Since the frequency division number N of the feedback frequency divider is an integer, the period of the output clock of the PLL is a fixed value of 1/N times the period of the reference input clock.
There are various types of configurations of the SSCG depending on its mode, and most of the configurations are similar to those of the PLL; the configuration in which the modulation is performed with the frequency division number of the feedback frequency divider constituting the PLL is commonly known.
In this case, the SSCG includes a phase comparator, a charge pump circuit, a low-pass filter, a voltage controlled oscillator, a feedback frequency divider, a ΔΣ modulator and a modulation wave generator.
The feedback frequency divider can switch the frequency division number between two types, that is, N and (N−1), selects a use ratio of the integer N and the integer (N−1) during a given time period to obtain as an average frequency division number a non-integral value between N and (N−1) and sequentially changes this use ratio to output as an output clock the SSC whose period is varied from a reference input clock having a constant period.
As this type of spread spectrum clock generator, there is known a spread spectrum clock generator including: for example, a PLL that outputs four-phase clocks whose phases are shifted by 90 degrees with each other; a phase interpolation control circuit that operates in synchronization with a reference clock and outputs control signals which periodically and repeatedly vary in a constant pattern according to each of the four-phase clocks and which assign weights between adjacent two-phase clocks among the four-phase clocks; a phase interpolator that assigns weights to each of the adjacent two-phase clocks according to the control signal for each of the adjacent two-phase clocks to combine them together, that interpolates the phase between them in a predetermined phase for all adjacent two-phase clocks and that outputs the clock obtained by interpolating the phase as a spread spectrum clock (see patent document 1 (Japanese Patent Laid-Open No. 2006-211208)).